(1) Field of the Invention
The present invention relates to a method and apparatus for reducing the size of memory arrays in an integrated circuit chip. More specifically, the present invention implements bit line sharing in highly parallel memory structures.
(2) Art Background
It is quite common for memory storage to comprise semiconductor memories organized in rectangular arrays of rows and columns on very-large-scale integrated (VLSI) circuits. The intersection of one row and one column results in a storage element called a "cell". Each cell is capable of storing a binary bit of data. To write data into, and to read data from, a row or column of cells, an address is assigned to each row or column of cells. Access to the address is provided in a binary-coded address presented as input to address decoders that select a row or column for a write or read operation.
Static random access memory (SRAM) is a form of semiconductor memory that is widely known and used. SRAM storage is based on the logic circuit known as the flip-flop, which retains the information stored in it as long as there is enough power to run the device. A typical SRAM cell consists of six transistors. Although each SRAM cell requires a large layout space, SRAM is employed in situations which require high-speed random access such as cache memory. In the usual SRAM design, each cell has one word line and two bit lines (BIT and BIT#) to access cells.
Another example of memory storage is content addressable memory (CAM) which is a memory-based storage method in which data items are accessed, not by reference to some fixed address or location, but by analysis of their content. CAM enables one to look up matched data at a very high speed without reading out the content of the memory. It is used particularly in small, high-speed cache devices in order to determine whether a virtual memory page (a special type of storage) is present. In the usual design, each CAM cell has two bit lines (BIT and BIT#). A usual CAM cell is comprised of 10 transistors and also requires a large layout space.